Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Date
10/04/2013
11/27/2013
02/07/2014
03/04/2014
Version
2.5
2.6
2.7
2.8
Description
In Table 1 , revised V IN (I/O input voltage) to match values in Table 4 and Table 5 , and combined Note 4
with old Note 5 and then added new Note 5 . Also in Table 1 , updated I DCIN and I DCOUT sections.
Revised V IN description and added Note 3 and Note 8 in Table 2 . Updated first 3 rows in Table 4 and
Table 5 . Replaced XPower with Xilinx Power Estimator (XPE) in sentence before Table 7 . Updated V IL
minimum for PCI33_3 in Table 9 . Added Note 1 to Table 12 . Added Note 1 to Table 13 . Added Vivado
Design Suite to AC Switching Characteristics . Updated titles of Table 18 and Table 19 , and removed
the following note: RLDRAM III (BL = 4, BL = 8) and LPDDR2 specifications have not been validated
with memory IP . Updated T IOOP and T IOTP values in Table 20 . Replaced “TRACE report” with “timing
report” in notes for Table 26 , Table 27 , Table 28 , Table 30 , and Table 32 . Removed this note: A Zero “0”
Hold Time listing indicates no hold time or a negative hold time from Table 30 , Table 31 , and Table 46 .
Updated Note 1 in Table 36 . Updated Table 58 to more accurately show transceiver user clocks for
supported line rates. Updated Note 8 and description of F GTXRX in Table 60 . Updated Note 2 , Note 3 ,
and Note 4 in Table 68 . Added T USRCCLKO to Table 69 .
Added Kintex-7Q defense-grade devices throughout. Added -1M speed grade throughout. Added
reference to 7 Series FPGAs Overview and Defense-Grade 7 Series FPGAs Overview in Introduction .
In Table 2 , added junction temperature operating range for military (M) devices. In Table 3 , removed
commercial (C), industrial (I), and extended (E) from descriptions of R IN_TERM . Updated temperature
ranges in Table 4 and Table 5 . Removed Note 1 and Note 2 from Table 7 . Added T J = 125°C to
Conditions column for T VCCO2VCCAUX in Table 8 . Added Table 14 . Updated description of
MMCM_F PFDMAX in Table 39 . Updated description of PLL_F PFDMAX in Table 40 . Added RF package
type to Table 54 . Added F DNACK to Table 69 .
Updated the AC Switching Characteristics based upon ISE 14.7 and Vivado 2013.4. Updated Note 5
and added Note 6 to Table 2 . Added Note 2 to Table 4 . Added Note 2 and updated Note 3 in Table 5 .
Added HSUL_12_F, DIFF_HSUL_12_F, MOBILE_DDR_S, MOBILE_DDR_F, DIFF_MOBILE_DDR_S,
and DIFF_MOBILE_DDR_F standards to and updated values in Table 20 . Added HSUL_12_F,
DIFF_HSUL_12_F, DIFF_HSUL_12_DCI_S, and DIFF_HSUL_12_DCI_F standards to and updated
values in Table 21 . In Table 33 , corrected F MAX_CAS_RF_DELAYED_WRITE from 478.27 to 478.24 MHz to
match software behavior. Removed introductory paragraph of Device Pin-to-Pin Output Parameter
Guidelines and Device Pin-to-Pin Input Parameter Guidelines . Updated display format of “ADC
Accuracy at Extended Temperatures” section in Table 68 .
Updated Note 2 in Table 4 and Note 2 in Table 5 . For XQ7K325T and XQ7K410T in Table 15 , changed
-2 and -1 speed grades to -2I and -1I, respectively, and moved all XQ7K325T speed grades from
Preliminary to Production. In Table 16 , added production software for XQ7K325T -2/2L, -1, -1M, and
(0.9V) -2L speed grades. Removed “and FB” from title of Table 19 . Removed notes from Table 20 and
Table 21 . Added Note 1 to Table 67 .
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DS182 (v2.8) March 4, 2014
Product Specification
62
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